Hybrid constraint-based test pattern generation

Abstract

The role of testing in Integrated circuit (IC) is to determine the correctness of manufactured circuits. Therefore, testing is important since the fraction of good chips sold in the market yields the quality of the product. Automatic test equipment (ATE) is equipment that used in manufacturing test. The advance in IC technology make the memory needed for ATE is big. However, this could be lessened by reducing the data volume inserted in the ATE. This could be achieved through test compaction like fault collapsing. In this research, hybrid constraint-based test pattern generation proposed that include fault injection, Automatic test pattern generation (ATPG) and fault simulation. The fault injection is creating the faulty circuits while the ATPG searching the test patterns. For the fault simulation, it calculates the fault coverage of the ATPG system. In the fault injection, the functional fault modeling adopted which applied the fault collapsing. This fault collapsing is aiding in test compaction. Five experiments being done on eight Circuit under tests (CUTs) from the International Torino Conference (ITC) '99 benchmark circuits. The high-level and gate-level fault coverage, and the test length for this CUTs have been obtained from this experiments. The average of compaction ratio that obtained by the proposed method is 5.42%.