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Verilog design of a 256-bit AES crypto processor core

Lai, Yit Pin (2007) Verilog design of a 256-bit AES crypto processor core. Masters thesis, Universiti Teknologi Malaysia, Faculty of Electrical Engineering.

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Abstract

The 21st Century is the Century of Digital, almost all of the information processing and telecommunication are in digital formats, therefore it is a must to ensure the digital data storage and transmission are secured, thus to ensure privacy. Cryptography is the practice to protect one’s information through encryption. As of today, the most widely used and studied algorithm is the Advanced Encryption Standard (AES) published 2001. AES algorithm is fast and easy to be implemented in both software and hardware; however software implementation is vulnerable due to loopholes in operating system and generally is less efficient than hardware implementation. This thesis proposes a design of 256-bit AES crypto-processor core in Verilog RTL, by extending from previous UTM student’s research, targeted at FPGA implementation in System-on-Chip (SoC) designs. This soft core is designed in compact form and generalized to comply with multiple AES specifications, which will be a valuable asset in UTM soft core IP bank that helps in future SoC researches.

Item Type:Thesis (Masters)
Additional Information:Thesis (Master of Engineering (Computer and Microeletronics System)) - Universiti Teknologi Malaysia, 2007; Supervisor : Prof. Dr. Mohamed Khalil b. Hj. Mohd. Hani
Uncontrolled Keywords:Cryptography, advanced encryption standard (AES), AES encryption processor core, Verilog HDL
Subjects:T Technology > TK Electrical engineering. Electronics Nuclear engineering
Q Science > QA Mathematics > QA76 Computer software
Divisions:Electrical Engineering
ID Code:6392
Deposited By: Ms Zalinda Shuratman
Deposited On:24 Sep 2008 00:50
Last Modified:09 Oct 2012 05:43

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