A linear array passively quenched single photon avalanche diode

Abstract

The integrated circuit design of Single Photon Avalanche Diode (SPAD) with quenching circuit in CMOS is highly desirable photon detection at high rates, but low counting rates constrain image acquisition rates and dynamic range. The characterization should primarily define the dead time of quenching SPAD circuit in order to estimate the SPAD performance prior fabrication. This paper reports the development and characterization of the mathematical model SPAD on passively quenched SPAD circuit with ballast resistor. An improved model in defining the dead time (tD) response for SPAD is used to characterize the performance of 8×1 passively quenched SPAD array. The time response for both quenching and recharging time are developed for 180 nm depletion layer which means low voltage technology. Hence that, the 8×1 passively SPAD array circuit is designed by using Silterra 180nm CMOS technology for uncorrelated time measurements with on-chip 4-bit counter to improve the counting rate. The passive quenching circuit design on-chip would enable the capability to perform at higher speed, which is more than 100 kHz. In addition, are presented in this paper.