Built-in self test power and test time analysis in on-chip networks

Abstract

Testing power dissipation of on-chip networks (NoC) is an interesting topic, which is still unexplored specially analytically. In this paper, a transistor level model is proposed to study the testing power and area of testing logic in a mesh NoC using IEEE 1149.1-based approach. For the purpose of verification, HSPICE simulation and FPGA implementation are used. The switching activities are computed using a special purpose cycle-accurate NoC simulator. At the end, the model is used to calculate test power and spot the most energy consuming and area occupying component of a typical NoC testing circuit.