Modeling of nanodevices and nanostructures

Abstract

Since its first development in more than half a century ago, the silicon-based transistors have been experiencing rapid growth following the trend known as Moore’s Law. The transistor scaling into nanometer regime has reached decananometer dimension since the last decade, which brings about the unprecedented complexities in the fabrication process, especially in the effort to keep pace with the technology projection. In addition, the conventional device structure that has been around for decades is extremely hard to be scaled further due to many limitations. These obstacles generate broad interests on novel device architectures as well as involvement of new materials other than silicon. The industry is already preparing for the postsilicon era, with the enormous researches in emerging materials such as III–V compounds, SiGe, and carbon as can be observed from the International Technology Roadmap for Semiconductor (ITRS)