Gate oxide short (gos) defect modeling based on 32 nm CMOS process

Abstract

Among the wide set of possible failure mechanisms in IC?s, Gate Oxide Short (GOS) defect is and has been a dominant mechanism failure for CMOS IC?s. It is difficult to detect the existence of GOS as it only causes marginal degradation in circuit?s performance due to small leakage current. If GOS occurs in SRAM, it causes data loss which may take time to be realized. A number of GOS models have been developed based on different CMOS process technologies, but there is a need to relook at their suitability in nano-scaled technology. There is also a need to reassess the observation point to make it more practical from application point of view. This work has two main phases; the first one is to explore a GOS defect model that can efficiently express the defect behaviour and the second one is to design a 6T transistors SRAM cell in 32 nm CMOS process technology and apply this model on the cell and then analyse its impact on the performance of SRAM cell. A non-linear non-split model is used in this work with some improvement to make it suitable in high speed circuits. T- Spice from Tanner Tools is used in all simulations. A modified non-linear non-split model for GOS has been developed and it was tested in three different locations (close to source/drain and in the middle) with different sizes of Rgos values: from 1 O to 1 MO. It was found that GOS which is close to drain is very difficult to be detected. From simulation in time domain, it was noted that GOS defect could be conveniently detected through gate current (IG) measurement of the defective transistor and this method is also more practical than the ordinary method of monitoring the drain current (ID)