A network-on-chip simulation framework for homogeneous multi-processor system-on-chip

Abstract

This paper presents a Network-on-Chip (NoC) simulation framework at the Electronic System Level (ESL) design abstraction based on SystemC. The proposed ESL NoC framework extends the NIRGAM NoC simulator by integrating ARM Instruction Set Simulator (ISS) as its application Intellectual Property (IP) cores. This enables the modelling of complex homogeneous Multi-Processor System-on-Chip (MPSoC) by simulating the behaviour of embedded cores using ISSs attached to NoC tiles. The actual traffic patterns are extracted according to the target application for NoC performance analysis. In this paper, we describe the development of the extended NoC framework which includes the definitions of synchronization and data communication protocol, interprocess communication module, network interface architecture design, and device driver. Experimental result shows that the extended platform enables early NoC-based MPSoC system functionality estimation and provides NoC performance analysis with higher accuracy by considering the actual traffic trace according to the target application.