Teoh, Giap Seng (2003) VHDL modelling and asic design of a shortest-path processor core for network routing. Masters thesis, Universiti Teknologi Malaysia, Faculty of Electrical Engineering.
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| Item Type: | Thesis (Masters) |
|---|---|
| Additional Information: | Thesis (Sarjana Kejuruteraan (Elektrik)) - Universiti Teknologi Malaysia, 2003 |
| Subjects: | T Technology > TK Electrical engineering. Electronics Nuclear engineering |
| Divisions: | Electrical Engineering |
| ID Code: | 42788 |
| Deposited By: | Haliza Zainal |
| Deposited On: | 02 Nov 2014 03:13 |
| Last Modified: | 30 Aug 2017 02:18 |
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