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Device and circuit-level performance of carbon nanotube field-effect transistor with benchmarking against a nano-MOSFET

Tan, Michael Loong Peng and Lentaris, Georgios and Amaratunga, Gehan A. J. (2012) Device and circuit-level performance of carbon nanotube field-effect transistor with benchmarking against a nano-MOSFET. Nanoscale Research Letters, 7 . ISSN 1931-7573

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Official URL: http://dx.doi.org/10.1186/1556-276X-7-467

Abstract

The performance of a semiconducting carbon nanotube (CNT) is assessed and tabulated for parameters against those of a metal-oxide-semiconductor field-effect transistor (MOSFET). Both CNT and MOSFET models considered agree well with the trends in the available experimental data. The results obtained show that nanotubes can significantly reduce the drain-induced barrier lowering effect and subthreshold swing in silicon channel replacement while sustaining smaller channel area at higher current density. Performance metrics of both devices such as current drive strength, current on-off ratio (Ion/Ioff), energy-delay product, and power-delay product for logic gates, namely NAND and NOR, are presented. Design rules used for carbon nanotube field-effect transistors (CNTFETs) are compatible with the 45-nm MOSFET technology. The parasitics associated with interconnects are also incorporated in the model. Interconnects can affect the propagation delay in a CNTFET. Smaller length interconnects result in higher cutoff frequency.

Item Type:Article
Uncontrolled Keywords:Benchmarking, Device modeling
Subjects:T Technology > TK Electrical engineering. Electronics Nuclear engineering
Divisions:Electrical Engineering
ID Code:33445
Deposited By: Fazli Masari
Deposited On:28 Aug 2013 04:11
Last Modified:30 Nov 2018 06:35

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