FPGA implementation of Image processing 2D convolution for spatial filter

Abstract

Computer manipulation of images is generally defined as digital image processing (DIP). DIP is used in variety of applications, including video surveillance, target recognition, and image enhancement. Some of the many algorithms used in image processing include convolution, edge detection and contrast enhancement. These are usually implemented in software but may use special purpose hardware for speed. With advances in the VLSI technology hardware implementation has become an attractive alternative. Assigning complex computation tasks to hardware and exploiting the parallelism and pipelining in algorithms yield significant speedup in running times. The main objective of this project is to develop an image processing algorithm, 2D convolution. The algorithm is designed and implemented in synthesizable Verilog HDL. Upon completion of the coding, its functionality and timing are then verified thoroughly. Subsequently, the performance of the 2D convolution is analyzed. The designed 2D convolution applies pipeline and parallel architecture for speedup and real-time applications. The entire design process starts with architecture definition and design. Once the required modules and functionalities such as DU and CU are defined, they are then coded and integrated. Verification is done from bottoms up starting from individual sub-modules. In addition, the design is further verified with real image pixels and compared the output pixels with that obtained from software (MATLAB). Altera Quartus II compilation report shows the 2D convolution design acheieves fmax as high as 394MHz using off-chip RAM. The performance is slighly degraded, to about 322MHz with on-chip RAM.