Finite impulse response filter design on distributed arithmetic architecture

Abstract

In signal and image processing application, highly repetitive operations and intense multiplication computation that exist in Digital Signal Processing systems makes it challenging to achieve less hardware requirement (area) and less latency (speed) performance using software based platforms, thus a lot of hardware design architecture becomes available to fill the gap. A close examination of the algorithms used in these, and related, applications reveals that many of these fundamental actions involve calculation of sum of products, vector dot product, inner product or multiply and accumulate (MAC). A study on the FIR filter involves multiply and accumulates operation where inner product forms the basis of the algorithms of the core. It is the aim of this paper to develop efficient architecture of a FIR filter on Distributed Arithmetic (DA) through ROM based ideally suited for efficient computation in order to achieve better performances in terms of speed and area by providing an effective methodology to implement MAC using a simple combination of memory elements, adders and shifters instead of lumped multipliers. The design is an 8-tap low pass filter based on 16-bit input samples and 16-bit signed coefficients at sampling frequency of 16MHz. All the coefficients are stored in the ROM 8x16 words size. The behavioural model of the FIR filter is structured in Verilog code and synthesized using Altera QuartusII version 11. The timing simulation is verified by running testbench codes written in Verilog using ModelSim 6.6d. The results from the simulation show that the FIR filter can be implemented using Distributed Architecture rather than using lumped multipliers.