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Design and analysis of a novel low pdp full adder cell

Ghadiry, M. H. and A'ain, Abu Khari and Nadi, M. (2011) Design and analysis of a novel low pdp full adder cell. Journal Of Circuits Systems And Computers, 20 (3). pp. 439-445. ISSN 0218-1266

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Official URL: http://dx.doi.org/10.1142/S0218126611007323

Abstract

This paper, presents a new full-swing low power high performance full adder circuit in CMOS technology. It benefits from a full swing XOR-XNOR module with no feedback transistors, which decreases delay and power consumption. In addition, high driving capability of COUT module and low PDP design of SUM module contribute to more PDP reduction in cascaded mode. In order to have accurate analysis, the new circuit along with several well-known full adders from literature have been modeled and compared with CADENCE. Comparison consists of power consumption, performance, PDP, and area. Results show that there are improvements in both power consumption and performance. This design trades area with low PDP.

Item Type:Article
Uncontrolled Keywords:full adder, high performance, Low PDP, low power, VLSI
Subjects:T Technology > TK Electrical engineering. Electronics Nuclear engineering
Divisions:Electrical Engineering
ID Code:28821
Deposited By: Liza Porijo
Deposited On:29 Nov 2012 04:53
Last Modified:29 Nov 2012 04:53

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