Universiti Teknologi Malaysia Institutional Repository

An FPGA hardware architecture of Nilsimsa fingerprinting algorithm

Monemi, A. and Mohamed, M. A. and Marsono, Muhammad Nadzir (2011) An FPGA hardware architecture of Nilsimsa fingerprinting algorithm. In: InECCE 2011 - International Conference on Electrical, Control and Computer Engineering. IEEE Explorer, pp. 124-129. ISBN 978-161284228-8

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Official URL: http:dx.doi.org/10.1109/INECCE.2011.5953862


Nilsimsa algorithm is a very effective spam fingerprinting technique. This spam fingerprinting algorithm is formulated for software implementation. In this paper, we present an FPGA hardware architecture of the modified form of Nilsimsa algorithm which has similar accurate with the original software-targeted algorithm. The modification results in hardware resources reduction and execution time speed up. The implemented algorithm works at 123 MHz frequency and has a throughput of 1 byte per 2 clock cycles (494 Megabits per second). Our system also needs an extra 512 clock cycles after receiving the entire of the message to compute the Nilsimsa fingerprint. This means the minimum time for computing the fingerprint of a message with the size of 10 Kbytes is 167 µ s, which is equal to 5988 emails per second. For 100 MHz clock, our proposed architecture is 1400 times faster compared to implementation on 32-bit general-purpose embedded processor, and 24 times faster than the implementation on a modern CPU running on 2.64 GHz clock.

Item Type:Book Section
Uncontrolled Keywords:fingerprinting, hardware implementation, nilsimsa, spam detection
Subjects:T Technology > TK Electrical engineering. Electronics Nuclear engineering
Divisions:Electrical Engineering
ID Code:28683
Deposited By: Liza Porijo
Deposited On:16 Nov 2012 06:56
Last Modified:04 Feb 2017 08:35

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