Verification of MEMS planar inductor

Abstract

The lack of an accurate model for on-chip inductors presents one of the most challenging problems for silicon- based radiofrequency integrated circuits (RF IC’s) designers. In conventional IC technologies, inductors are not considered as standard components like transistors, resistors, or capacitors, whose equivalent circuit models are usually included in the process description. However, this situation is rapidly changing as the demand for RF IC’s continues to grow [1]–[8]. Various approaches for modeling inductors on silicon have been reported in past several years [5]–[8]. Most of these models are based on numerical techniques, curve fitting, or empirical formulae, and therefore are relatively inaccurate or not scalable over a wide range of layout dimensions and process parameters. For inductor design insights and optimization, a compact, physical model is required. Some techniques and structures have been introduced for developing the high quality factor for MEMS inductors.