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Reduced parasitic capacitances analysis of nanoscale vertical MOSFET

Ismail, Razali and I., Saad and M. A., Riyadi and F. M., Zul Atfyi (2010) Reduced parasitic capacitances analysis of nanoscale vertical MOSFET. In: IEEE International Conference on Semiconductor Electronics, Proceedings, ICSE, 2010, Mallaca City, Malaysia.

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Official URL: http://dx.doi.org/10.1109/SMELEC.2010.5549485

Abstract

Quantitative comparison analysis was made between standard vertical MOSFET, vertical MOSFET with FILOX (Fillet Local Oxidation) and vertical MOSFET that combine ORI (Oblique Rotating Implantation) and FILOX technology. Due to a very thin gate oxide separated the gate track and source/drain electrode in standard vertical MOSFET, tremendous increase effects of gate-to-drain and gate-to-source parasitic capacitances was observed. The FILOX device was found to have a lower gate-to-source capacitance compared to FILOX + ORI device due to titled implants used in ORI for self-aligned S/D region formation and SCE control. Thus, thicker oxide on the top and bottom of silicon pillar or so-called FILOX structure has significantly reduce the intrinsic gate capacitance. However, with the addition of titled implants in FILOX + ORI device, the gate-to-drain capacitance has been significantly reduced while has a small difference (10 - 15%) of reducing gate-to-source capacitance as compared to FILOX device. Therefore, the addition of ORI method can suppress the effect of intrinsic gate capacitances and deliberately control the SCE with the self-aligned S/D region onto silicon pillar as scaling the device into nanometer realm.

Item Type:Conference or Workshop Item (Paper)
Subjects:T Technology > TK Electrical engineering. Electronics Nuclear engineering
Divisions:Electrical Engineering
ID Code:27945
Deposited By: Liza Porijo
Deposited On:29 Aug 2012 05:35
Last Modified:29 Aug 2012 05:39

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