Ismail, Razali and M. A., Riyadi and J. E., Suseno and Z. A. F. M., Napiah and A. M. A., Hamid and I., Saad (2010) Investigation of short channel immunity of fully depleted double gate MOS with vertical structure. In: IEEE International Conference on Semiconductor Electronics, Proceedings, ICSE, 28-30 June 2010, Melaka, Malaysia.
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Official URL: http://dx.doi.org/10.1109/SMELEC.2010.5549479
The electrical performance of fully depleted double gate MOSFET devices with vertical structure feature were evaluated with the implementation of oblique rotating implantation (ORI) method for several silicon pillar thicknesses using virtual wafer tool. The difference in the subthreshold performance is well noticed, as well as the potentials across the channel for different geometries. The implication of channel length reduction shows that in fully depleted feature, thinner pillar will result in better subthreshold performances than the thicker structure while maintaining the high on-current. As a result, thinner pillar delivers better short channel characteristic control in further channel scaling up to 20 nm.
|Item Type:||Conference or Workshop Item (Paper)|
|Subjects:||T Technology > TK Electrical engineering. Electronics Nuclear engineering|
|Deposited By:||Liza Porijo|
|Deposited On:||29 Aug 2012 03:29|
|Last Modified:||05 Feb 2017 08:18|
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