Modeling and Characterization of Majority (MAJ) type Single-Electron Full Adder using SIMON

Abstract

Single Electron Transistor (SET), distinguished by a very small device size and low power dissipation, is one of the most promising nanoelectronic devices to replace conventional CMOS. It is based on controlling the transport of an individual electron. This paper focuses on the modeling and characterization of majority (MAJ) type SET full adder (FA) which is based on threshold logic gates (TLGs). An adder is very important, both as stand-alone unit and as a basis for other units such as program counters, multipliers, and memory addressing units. To model and characterize MAJ type SET full adder, few other circuits are modeled and analyzed which are single device SET, SET inverter and SET MAJ gate circuits. All the circuits are characterized using SIMON 2.0 simulator. The number of components for a MAJ type SET full adder circuit is 57 which consist of 37 capacitors and 20 tunnel junctions. The circuit is functioning as required for all the combination of input voltage. Since the full adder model is based on MAJ function, the stability of the SET inverter is an important aspect of the MAJ design because of the sensitivity of circuit tends to switch threshold value. In order to achieve stability, the input voltage must be in step function. The output waveform for this MAJ type FA is regular for all the combinations of inputs since the output–input (Vo/Vi) ratios is higher than 80% for both sum and carry–out outputs.