Universiti Teknologi Malaysia Institutional Repository

Multilever inverter topologies

Abdul Aziz, Junaidi and Salam, Zainal (2008) Multilever inverter topologies. In: Recent Advances In Power Inverter. Penerbit UTM , Johor, pp. 165-179. ISBN 978-983-52-0647-4


Official URL: http://www.penerbit.utm.my/bookchapterdoc/FKE/book...


Multilevel voltage source inverter (MVSI) is very attractive in high voltage and high power applications such as adjustable speed drives and electric utility applications. The development of MVSI began in the early 1980’s when Nabae et al. [1] proposed a neutralpoint clamped (NPC) PWM inverter. Since then several multilevel topologies have evolved. The general structure of the MVSI is to synthesize a sinusoidal voltage out of several levels of dc voltages [2]. The so-called multilevel inverter starts from three levels. The MVSI can therefore be described as a voltage synthesizer. . There are several advantages offered by the MVSI. In Voltage Source Inverter (VSI), the maximum voltage level output is determined by the voltage blocking capability of each device. By using a multilevel structure, the stress on each device can be reduced in proportional to the number of levels, thus the inverter can handle higher voltages [3]. As a result, an expensive and bulky step-up transformer can be avoided in various applications. In another perspective, the harmonic in the output waveform can be reduced without increasing switching frequency or decreasing the inverter power output [4]. As the number of voltage levels reach infinity, harmonic content will be low enough to avoid the need of filters [5]. The number of the achievable voltage levels, however is limited by voltage unbalance problems, voltage clamping requirement, circuit layout, and packaging constraints. In motor application, high dV/dt in power supply generates high stress on motor windings and requires additional motor insulation. Furthermore, high dV/dt of semiconductor devices increases the electromagnetic interference (EMI), common-mode voltage and possibility of failure on motor. With several levels in output waveform constructed by multilevel inverter, the switching dV/dt stresses are reduced [4].

Item Type:Book Section
Subjects:T Technology > TK Electrical engineering. Electronics Nuclear engineering
Divisions:Electrical Engineering
ID Code:24931
Deposited By: Zalinda Shuratman
Deposited On:27 Apr 2012 08:39
Last Modified:10 Oct 2017 01:36

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