A'Ain, Abu Khari and Khor, J. G. and Bong, Dennis Yuan Yiunn (2010) Scalable Test Pattern Generation (STPG). In: 2010 IEEE Symposium on Industrial Electronics & Applications, 3-6 October 2010, Pulau Pinang.
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Official URL: http://dx.doi.org/10.1109/ISIEA.2010.5679428
Abstract
Traditional test pattern generation (TPG) is a well known technique that has been used by many to generate test sequence. With increasing number of chip inputs, larger the test vector is required to ensure high fault coverage is achieved. This adds additional cost in traditional TPG generation and becomes a concern. In this paper, we introduce a new test generation method that is scalable while manages to produce high fault coverage. An attractive feature of the proposed method is it is able to sample the test signature early.
| Item Type: | Conference or Workshop Item (Paper) |
|---|---|
| Uncontrolled Keywords: | Anti-random (AR), Hamming Distance (HD), Linear Feedback Shift Register (LFSR), Test Pattern Generation TPG) |
| Subjects: | T Technology > TK Electrical engineering. Electronics Nuclear engineering |
| Divisions: | Electrical Engineering |
| ID Code: | 24241 |
| Deposited By: | Liza Porijo |
| Deposited On: | 06 Aug 2012 07:49 |
| Last Modified: | 06 Aug 2012 07:51 |
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