Design of an advanced encryption standard crypto-processor core for field programmable gate array implementation

Abstract

Cryptographic applications becoming increasingly more important in today’s world of data exchange. Big volume data needs to be transferred from one location to another through communication path but exposes to attackers. Cryptography services are essential in order to provide the authentication, privacy, non-repudiation and integrity of private data being transmitted. System-on-Chip (SoC) technology enters the mainstream in digital design. The advances in reconfigurable hardware create the possibility of developing a microchip with application-specific processors. The processors perform their respective dedicated algorithm-intensive computations. This thesis presents the architecture for implementation of the new Advanced Encryption Standard (AES) in hardware for operating under SoC environment. The proposed AES Crypto-Processor accelerates the AES algorithm in reconfigurable Field Programmable Gate Arrays (FPGA). The processor design is completely described in hardware description language, VHDL. When designing hardware, the desire is often to achieve the highest performance possible. With implementation on Altera’s APEX FPGA, experimental evaluation of the AES Crypto-Processor running at 50 MHz using test vector provided in FIPS (2002) yields an average encryption rate at 188.24 Mb/s and decryption rate at 200 Mb/s which makes the overall performance is at 192.12 Mb/s. The design uses only 3,355 logic elements or 31% of hardware resources. The result of this work is the first step to the ultimate goal of developing a complete cryptographic system processor for security application in embedded system design