Tunable level-shifter / buffer for dual supply systems and low-power clock-tree design in deep-submicron apllication

Abstract

A new architecture for analog tunable level-shifter is introduced in the 130 nm CMOS process. As the transistor keeps on shrinking, low power design becomes more challenging. Dual supplies are used for many low-power applications and needs level-shifter between the low Vdd and high Vdd critical path. Similarly, although the die sizes are shrinking but the high speed I/Os are relatively larger and hence use higher Vdd supply, and hence needs level-shifters in between the core and the I/O circuits. Also the clock trees are major source for power dissipation in present day high-speed design. Reducing the clock swings within the tree and the branches can help reduce the overall power dissipation for the chip. The new tunable-level shifter takes in different input voltages and shifts it to 1.2 V-1.5 V outputs. The input voltage can range from 0.45 V to Vdd, while the threshold for the shifter is tuned using a reference-voltage, thus controlling the current through the level-shifter/buffer. Modification has been done to the circuit for low-power application with minimal degradation to the performance.