Rajah, Avinash and Hani, Mohamed Khalil (2004) Asic design of a kohonen neural network microchip. In: Proceedings ICSE 2004 - 2004 IEEE International Conference on Semiconductor Electronics. IEEE, USA, pp. 148-151.
- Published Version
Official URL: http://dx.doi.org/10.1109/SMELEC.2004.1620857
This paper discusses the Kohonen neural network (KNN) processor and its KNN computation engine microchip. The ASIC design of the KNN processor adopts a novel implementation approach whereby the computation of the KNN algorithm is performed on the custom ASIC microchip and its operations are governed by a FPGA based controller. Thus, the ASIC implementation of the KNN processor is derived through integration between a custom ASIC and FPGA. The 3.3V AMI 0.5um CO5M-D process technology was used to achieve the VLSI design of the computation engine microchip and the entire design adopted the BBX cell based methodology, which is a viable alternative to conventional ASIC methodology.
|Item Type:||Book Section|
|Additional Information:||ISBN: 0780386582; 978-078038658-7 2004 IEEE International Conference on Semiconductor Electronics, ICSE 2004, 4-9 Dec. 2004, Kuala Lumpur.|
|Uncontrolled Keywords:||application specific integrated circuits, computer networks, design, electric conductivity, field programmable gate arrays (FPGA), image classification, image segmentation, neural networks, process engineering, semiconductor materials, international conferences, kohonen neural networks, semiconductor electronics, integrated circuits|
|Subjects:||T Technology > TK Electrical engineering. Electronics Nuclear engineering|
|Deposited By:||Dr Zaharuddin Mohamed|
|Deposited On:||21 Mar 2007 08:37|
|Last Modified:||18 Dec 2013 03:29|
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