Seif, Aramesh (2009) A hardware architecture of prewitt edge detection. Masters thesis, Universiti Teknologi Malaysia, Faculty of Electrical Engineering.
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The objective of this project is to develop a real-time hardware architecture for Prewitt edge detection algorithm. Prewitt edge detection provides differencing operation in the single kernel. Verilog hardware description language was used as the hardware programming language for a real-time edge detection system. The architecture is capable of operating with a clock frequency of 145 MHz at 550 frames per second. Computation error analysis performed shows that the proposed architecture produces outputs similar to that obtained by software simulation using Matlab.
|Item Type:||Thesis (Masters)|
|Additional Information:||Supervisor : Dr. Muhammad Nadzir Marsono; Thesis (Sarjana Kejuruteraan (Elektrik-Elektronik dan Telekomunikasi)) - Universiti Teknologi Malaysia, 2009|
|Uncontrolled Keywords:||Image processing, Verilog hardware|
|Subjects:||T Technology > TK Electrical engineering. Electronics Nuclear engineering|
|Deposited By:||Kamariah Mohamed Jong|
|Deposited On:||08 Aug 2012 00:02|
|Last Modified:||08 Aug 2012 00:08|
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