Universiti Teknologi Malaysia Institutional Repository

Verilog design of bist on AES256 processor core with FPGA implementation

Hew, Kean Yung (2008) Verilog design of bist on AES256 processor core with FPGA implementation. Masters thesis, Universiti Teknologi Malaysia, Faculty of Electrical Engineering.

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Cryptography is very important to ensure secured data storage and transmission through encryption technique in this digital world. The most widely used cryptography algorithm is the Advanced Encryption Standard (AES) published in 2001. AES algorithm is fast and easy to be implemented, and it aims to protect data and ensure privacy. Hence, AES hardware cannot afford any encryption failure which will corrupt the whole system. Built-In-Self-Test (BIST) introduced into the AES system will increase the system testability and reliability, which in turn will protect the system from attack and will incur less testing cost. This project aims to continue previous UTM student’s research on FPGA implementation of AES system in System-on-Chip (SoC) design. By extending further, a proposed AES hardware BIST design is incorporated into the AES processor core in Verilog RTL and FGPA implementation. This will be a valuable asset to UTM for future SoC researches on AES and BIST design.

Item Type:Thesis (Masters)
Additional Information:Thesis ( Sarjana Kejuruteraan (Elektrik - Komputer dan Mikroelektronik )) - Universiti Teknologi Malaysia, 2008; Supervisor : Prof. Dr. Mohamed Khalil Mohd. Hani
Uncontrolled Keywords:verilog (computer hardware description language), field programmable gate arrays
Subjects:T Technology > TK Electrical engineering. Electronics Nuclear engineering
Divisions:Electrical Engineering
ID Code:18136
Deposited By: Kamariah Mohamed Jong
Deposited On:29 Apr 2014 01:57
Last Modified:29 Apr 2014 01:57

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