Universiti Teknologi Malaysia Institutional Repository

Verilog design of bist on AES256 processor core with FPGA implementation

Hew, Kean Yung (2008) Verilog design of bist on AES256 processor core with FPGA implementation. Masters thesis, Universiti Teknologi Malaysia, Faculty of Electrical Engineering.

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Item Type:Thesis (Masters)
Additional Information:Supervisor : Prof. Dr. Mohamed Khalil Mohd. Hani; Thesis ( Sarjana Kejuruteraan (Elektrik - Komputer dan Mikroelektronik )) - Universiti Teknologi Malaysia, 2008
Subjects:T Technology > TK Electrical engineering. Electronics Nuclear engineering
Divisions:Electrical Engineering
ID Code:18136
Deposited By: Kamariah Mohamed Jong
Last Modified:18 Nov 2011 04:31

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