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Silicon pillar thickness effect on vertical double gate MOSFET (VDGM) with oblique rotating implantation (ORI) method

A. Riyadi, Munawar and Saad, Ismail and Ismail, Razali (2008) Silicon pillar thickness effect on vertical double gate MOSFET (VDGM) with oblique rotating implantation (ORI) method. In: IEEE International Conference on Semiconductor Electronics (ICSE 2008), 2008, Johor Bahru, Johor.

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Official URL: http://dx.doi.org/10.1109/SMELEC.2008.4770367

Abstract

The silicon pillar thickness effect on vertical double gate MOSFET (VDGM) fabricated by implementing oblique rotating ion implantation (ORI) method is investigated. For this purpose, several silicon pillar thicknesses tsi were simulated. The source region was found to merge at tsi < 57 nm, forming floating body effect. The electron-hole concentration along the channel and the depletion isolation region shows different shape and broaden in smaller tsi. For several channel lengths Lg les 100 nm, in the reduction of pillar thickness, the subthreshold slope (SS) tends to decrease, which indicate an increase in gate-gate charge coupling. Other short channel effect parameters (Ioff, IDsat) show better improvement for lower pillar thickness, thus offer better performance and control.

Item Type:Conference or Workshop Item (Paper)
Subjects:T Technology > TK Electrical engineering. Electronics Nuclear engineering
Divisions:Electrical Engineering
ID Code:16885
Deposited By: Liza Porijo
Deposited On:31 Oct 2011 09:10
Last Modified:31 Oct 2011 09:10

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