Silicon pillar thickness effect on vertical double gate MOSFET (VDGM) with oblique rotating implantation (ORI) method

Abstract

The silicon pillar thickness effect on vertical double gate MOSFET (VDGM) fabricated by implementing oblique rotating ion implantation (ORI) method is investigated. For this purpose, several silicon pillar thicknesses tsi were simulated. The source region was found to merge at tsi < 57 nm, forming floating body effect. The electron-hole concentration along the channel and the depletion isolation region shows different shape and broaden in smaller tsi. For several channel lengths Lg les 100 nm, in the reduction of pillar thickness, the subthreshold slope (SS) tends to decrease, which indicate an increase in gate-gate charge coupling. Other short channel effect parameters (Ioff, IDsat) show better improvement for lower pillar thickness, thus offer better performance and control.