Universiti Teknologi Malaysia Institutional Repository

Short channel effects of SOI vertical sidewall MOSFET’s

Suseno, Jatmiko E. and Riyadi, Munawar A. and Ismail, Razali (2008) Short channel effects of SOI vertical sidewall MOSFET’s. In: IEEE International Conference on Semiconductor Electronics (ICSE 2008), 2008, Johor Bahru, Johor.

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Official URL: http://dx.doi.org/10.1109/SMELEC.2008.4770370


Application of asymmetric sidewall vertical metal oxide semiconductor field effect transistors (MOSFETs) is hindered by the parasitic overlap capacitance associated with their layout, which is considerably larger than for a lateral MOSFET on the same technology node. A simple process simulation has been developed to reduce the parasitic overlap capacitance in the asymmetric sidewalls vertical MOSFETs by using SOI (silicon on insulator) in bottom planar surfaces side. The result shows that while channel length decreases, the threshold voltage goes lower, the DIBL rises and subthreshold swing tends to decrease, for both structures. It is noted that the SVS MOSFET structure generally have better performance in SCE control compared to bulk vertical MOSFET. The presence of buried oxide is believed to increase the performance of vertical MOSFET, essentially in controlling the depletion in subthreshold voltage.

Item Type:Conference or Workshop Item (Paper)
Uncontrolled Keywords:SOI, sidewall, parasitic capacitance, vertical MOSFETs
Subjects:T Technology > TK Electrical engineering. Electronics Nuclear engineering
Divisions:Electrical Engineering
ID Code:16884
Deposited By: Mrs Liza Porijo
Deposited On:31 Oct 2011 09:08
Last Modified:07 Feb 2017 08:02

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