A. Riyadi, Munawar and Fauzan M. N., Zul Atfyi and Saad, Ismail and Ismail, Razali (2008) Characterization analysis of a novel approach in fabrication of CMOS compatible vertical mosfets incorporating a dielectric pocket. In: IEEE International Conference on Semiconductor Electronics (ICSE 2008), 2008, Johor Bahru, Johor.
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Official URL: http://dx.doi.org/10.1109/SMELEC.2008.4770407
The process of making novel CMOS compatible vertical MOSFET by incorporating Dielectric Pocket (DP) is shown using virtual wafer simulation tool. The corresponding device doping profiles of a junction is highlighted and demonstrated good device profiles for the feasibility of the approach. The effect of amorph Si recrystallization as the result of different RTA time is also evaluated. Both the transfer and output characteristics of the DP vertical MOSFETs indicates a reasonable value of drive and off -leakage current (ION and IOFF), sub-threshold swing (S) and Drain Induced Barrier Lowering (DIBL). The increasing time of RTA to 100 s shows better performance of the device than for shorter time, but in the thread-off of higher drain junction depth and leakage current.
|Item Type:||Conference or Workshop Item (Paper)|
|Subjects:||T Technology > TK Electrical engineering. Electronics Nuclear engineering|
|Deposited By:||Liza Porijo|
|Deposited On:||31 Oct 2011 08:49|
|Last Modified:||07 Feb 2017 06:50|
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