Fujiwara, Hideo and Iwata , Hiroyuki and Yoneda, Tomokazu and Ooi, Chia Yee (2008) A non-scan design-for-testability method for register-transfer level circuits to guarantee linear-depth time expansion models. In: IEEE Trans. On Computer-Aided Design of Integrated Circuits and Systems, 2008, France.
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Official URL: http://dx.doi.org/10.1109/TCAD.2008.927757
This paper presents a nonscan design-for-testability (DFT) method for register-transfer-level (RTL) circuits. We first introduce the notation to analyze the test generation complexity, as well as two classes of sequential circuits, namely: 1) the combinationally testable class and 2) the acyclically testable class. Then, we introduce a new class of linear-depth time-bounded circuits as one of the acyclically testable classes. The linear-depth time-bounded testability guarantees that the number of time frames required for any testable fault is bounded by a linear function of the number of flip-flops in the circuit during the test generation process. As one of the linear-depth time-bounded classes, we introduce a new class of RTL circuits, called the cycle-unrollable RTL circuits, which is shown to be linear depth time bounded. We propose a DFT method to make RTL circuits cycle unrollable and a test generation method for cycle-unrollable RTL circuits. Experimental results show that we can drastically reduce hardware overhead and test application time compared to the full-scan method and the method proposed by Ohtake Moreover, our proposed method can achieve 100% fault efficiency for gate-level single stuck-at faults in practical test generation time and allow at-speed testing.
|Item Type:||Conference or Workshop Item (Paper)|
|Uncontrolled Keywords:||acyclic testability, at-speed testing, design for testability, register transfer level (RTL), test generation complexity|
|Subjects:||T Technology > TK Electrical engineering. Electronics Nuclear engineering|
|Deposited By:||Liza Porijo|
|Deposited On:||31 Oct 2011 07:32|
|Last Modified:||07 Feb 2017 07:24|
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