Universiti Teknologi Malaysia Institutional Repository

Hardware-based biometric encryption implementation with Gauss-Jordan algorithm accelerator core in field programmable gate arrays

Liew, Tek Yee (2011) Hardware-based biometric encryption implementation with Gauss-Jordan algorithm accelerator core in field programmable gate arrays. Masters thesis, Universiti Teknologi Malaysia, Faculty of Electrical Engineering.

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Abstract

Modern security systems mostly utilize cryptographic scheme or biometric technology, each with its own vulnerabilities that degrade the security level. Biometric encryption (BE) provides higher security because it reaps the benefits from both mechanisms. Since BE is a complex system, a powerful personal computer (PC) is demanded to implement the system, although its mobility and portability are greatly reduced. This thesis proposes a hardware-based BE system implemented in Field Programmable Gate Array (FPGA). The design of the proposed BE system is based on the fuzzy vault scheme. One of the most critical function in the fuzzy vault scheme is the polynomial reconstruction which is based on the compute-intensive Gauss-Jordan Elimination algorithm. In this thesis, a hardware accelerator is proposed for this algorithm to enhance the timing performance of the BE system. The proposed BE system is implemented, together with finger-vein minutiae extraction subsystem and an Advanced Encryption Standard (AES) cryptographic subsystem, in an System-on-Chip (SoC) prototype for deployment in strong authentication data security application. The finger-vein minutiae extraction subsystem takes raw finger-vein image, processes, extracts and produces minutiae template for BE system while the cryptographic engine encrypts and decrypts the secret message. The BE system in turn takes cryptographic key and finger-vein minutiae template to combine them irrecoverably. The output of BE system is a secure vault template which leaks neither cryptographic key nor fingervein minutiae. The system is prototyped on an Altera development board running at 100MHz clock rate. Experimental results show that the hardware-based BE system achieved relatively high matching accuracy with 0.8% False Acceptance Rate and 18% False Rejection Rate and the timing performance gain is 10 times over the software prototype on embedded system. The SoC prototype is successfully deployed in an emulation of a biometric Automated Teller Machine.

Item Type:Thesis (Masters)
Additional Information:Thesis (Sarjana Kejuruteraan (Elektrik)) - Universiti Teknologi Malaysia, 2011; Supervisor : Prof. Dr. Mohamed Khalil Mohd. Hani
Subjects:T Technology > TK Electrical engineering. Electronics Nuclear engineering
Divisions:Electrical Engineering
ID Code:16456
Deposited By: Ms Zalinda Shuratman
Deposited On:28 Aug 2012 04:35
Last Modified:02 Apr 2013 01:09

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