Universiti Teknologi Malaysia Institutional Repository

The development of vertical MOSFET model incoporating a dielectrical pocket (DP)

Nurul Ezaila, Nurul Ezaila and Suseno, Jatmiko E. and Fauzan M. N., Zul Atfyi and Saad, Ismail and Ismail, Razali (2009) The development of vertical MOSFET model incoporating a dielectrical pocket (DP). In: The 25th Regional Conference on Solid State Science and Technology (RCSSST 2009). , 2009, Bayview Beach Resort, P. Pinang.

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Abstract

Vertical MOSFET has been named as a potential candidate for nanometer scale devices, to overcome the limitation of lithography and the complexity in planar devices. A structure of vertical MOSFET incorporating some novel features is revealed, namely dielectric pocket (DP) for suppression of short channel effects (SCEs). This research work is categorized into two parts; simulation using Silvaco software and device model using SPICE. The design issues of the device are addressed by using numerical simulation software which is the Silvaco’s Virtual Wafer Fab for the process and device simulation. Physical parameters are extracted from the I-V curve in order to analyze the threshold voltage roll-off (Vt), drain induced barrier lowering (DIBL), current ratio (Ion/ Ioff), and Sub-threshold swing. The model allows some optimization of performance from circuit perspective. Therefore, a device model of Vertical MOSFET is proposed containing a dielectric pocket by using SPICE (BSIM3v3.2.2 model card). The electrical model mentioned here is a circuit representation that has the electrical properties and characteristics of the component. The main objective of developing the model is to enable an accurate prediction of circuit performance. The electrical characteristic (I-V curve) of the device model will be analyzed and will be compared with the simulation results. The dielectric pocket structure that is being incorporated between the channel and drain is used to control encroachment of the drain doping into the channel and reduce short channel effects (SCE). The device model should be able to interpret the Vertical MOSFET device behaviours. The device model results obtained (I-V characteristics) should match with the simulation results. Therefore, a more accurate model can be obtained by including several parasitic components which are not considered in the existing model.

Item Type:Conference or Workshop Item (Paper)
Subjects:T Technology > TK Electrical engineering. Electronics Nuclear engineering
Divisions:Electrical Engineering
ID Code:15842
Deposited By: Liza Porijo
Deposited On:12 Oct 2011 08:20
Last Modified:12 Oct 2011 08:20

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