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Nano-CMOS circuit design and performance evaluation by inclusion of ballistic transport processes

Chek, Desmond C. Y. and Tan, Michael L. P. and Arora , Vijay K. (2009) Nano-CMOS circuit design and performance evaluation by inclusion of ballistic transport processes. In: Proceedings of the IEEE International Semiconductor Device Research Symposium 2009 (ISDRS), 2009, University of Maryland, College Park, Maryland, USA.

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Official URL: http://dx.doi.org/10.1109/ISDRS.2009.5378261

Abstract

The scaling of channel length and width in a nanoscale n-type MOSFET (NMOS) and ptype MOSFET (PMOS) is examined in ballistic (B) nano-CMOS design. The ballistic process is predominant in a nanoscale device when channel length is shorter than the mean free path. Our predictive model agrees well with 45nm experimental data from IBM. It is shown that the mobility is lower in the short channel device compared to the mobility in the long channel device due to the ballistic process.

Item Type:Conference or Workshop Item (Paper)
Subjects:T Technology > TK Electrical engineering. Electronics Nuclear engineering
Divisions:Electrical Engineering
ID Code:15479
Deposited By: Liza Porijo
Deposited On:30 Sep 2011 09:51
Last Modified:30 Sep 2011 09:51

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