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Numerical simulation characterization of 50nm MOSFET incorporating dielectric pocket (DP-MOSFET)

Fauzan, Zul Atfyi and Saad , Ismail and Ismail, Razali (2007) Numerical simulation characterization of 50nm MOSFET incorporating dielectric pocket (DP-MOSFET). In: International Coference on Advancement of Materials and Nanotechnology 2007 (ICAMN 2007), 2007, Langkawi.

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Official URL: http://dx.doi.org/10.1063/1.3377887

Abstract

10.1063/1.3377887Characterization of a metal-oxide-semiconductor field effect transistor incorporating dielectric pocket (DP) for suppression of short-channel effect (SCE) is demonstrated by using numerical simulation. An analysis of different uniform body doping from 1017 cm-3 to 1019 cm-3 of 50 nm channel length (Lg) with DP incorporated between the channel and source/drain has been done successfully. The DP has suppressed short channel effect (SCE) without the needs of decreasing the junction depth. A reduction of leakage current (IOFF) was obtained in MOSFET with DP without altering the drive current (ION). A very low leakage current is obtained for DP device with drain voltage (VDS) of 0.1 V. Consequently, the threshold voltage (VT) is increase accordingly with the increasing of body doping. A better control of VT roll-off was also demonstrated better for MOSFET with DP compare to conventional MOSFET. Thus, the incorporation of DP will enhance the electrical performance and give a very good control of the SCE for scaling the MOSFET in nanometer regime for future development of nanoelectronics product.

Item Type:Conference or Workshop Item (Paper)
Uncontrolled Keywords:MIS devices, field effect transistors, nanostructured materials, field effect devices, bipolar transistors, nanotube devices
Subjects:T Technology > TK Electrical engineering. Electronics Nuclear engineering
Divisions:Electrical Engineering
ID Code:14250
Deposited By: Liza Porijo
Deposited On:22 Aug 2011 01:51
Last Modified:22 Aug 2011 01:51

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