Universiti Teknologi Malaysia Institutional Repository

Numerical simulation analysis of CMOS compatible process of 50nm vertical single and double gate MOSFET

Saad, Ismail and Ismail, Razali (2007) Numerical simulation analysis of CMOS compatible process of 50nm vertical single and double gate MOSFET. In: International Coference on Advancement of Materials and Nanotechnology 2007 (ICAMN 2007), 2007, Langkawi.

Full text not available from this repository.

Abstract

Vertical MOSFET's have been proposed in the roadmap of semiconductor as a candidate for sub-100 nm CMOS technologies. In this paper, unique architecture of single and double gate vertical NMOS transistor is proposed that retained its CMOS compatibility. The MOSFET was fabricated by using oblique rotating ion implantation (ORI) technique addressed by numerical simulation. An electrical characterization of the device demonstrated a suppression of short channel effects (SCE) that was quantitatively given by an analysis of transfer and output characteristics with a reasonable value of threshold voltage (VT), drive and off -leakage current (ION and IOFF), saturation current (IDSat), subthreshold swing (S) and Drain Induced Barrier Lowering (DIBL). These results show that the vertical transistor is seen to offer considerable advantages down to the 100 nm node and beyond due to the dual or surround channels and the ability to produce a 50 nm channel length with relax lithography.

Item Type:Conference or Workshop Item (Paper)
Uncontrolled Keywords:Numerical simulation analysis, CMOS, MOSFET
Subjects:T Technology > TK Electrical engineering. Electronics Nuclear engineering
Divisions:Electrical Engineering
ID Code:14249
Deposited By: Mrs Liza Porijo
Deposited On:23 Aug 2011 05:53
Last Modified:12 Sep 2017 08:09

Repository Staff Only: item control page