Riyadi, Munawar A. and Saad, Ismail and Ahmadi, M. Taghi and Ismail, Razali and Rusop, Mohamad and Soga, Tetsuo (2009) Vertical double gate MOSFET for nanoscale device with fully depleted feature. In: AIP Conference Proceedings. Institute of Electrical and Electronics Engineers, New York, pp. 248-252. ISBN 978-073540673-5
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Official URL: http://dx.doi.org/10.1063/1.3160141
A fully depleted vertical double gate MOSFET device was revealed with the implementation of oblique rotating implantation (ORI) method in 25 nm silicon pillar thickness. Several devices with various gate lengths (20 - 100 nm) were simulated and evaluated using virtual wafer tool. The implication of gate length reduction on the short channel effect (SCE) shows considerable advantages with higher current drives at lower gate length, while the low subthreshold swing could balance the threshold voltage roll-off in the term of increasing power consumption. As a result, the drive current and also SCE controllability will be a benefit in the fully depleted device.
|Item Type:||Book Section|
|Additional Information:||International Conference on Nanoscience and Nanotechnology, Nano-SciTech 2008; Selangor; 18 November 2008 through 21 November 2008|
|Uncontrolled Keywords:||fully depleted, nanoscale, ori method, short channel effect, vertical MOSFET|
|Subjects:||T Technology > TK Electrical engineering. Electronics Nuclear engineering|
|Deposited By:||Liza Porijo|
|Deposited On:||20 Jul 2011 08:56|
|Last Modified:||20 Jul 2011 08:56|
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