Universiti Teknologi Malaysia Institutional Repository

An optimization algorithm based on grid-graphs for minimizing interconnect delay in VLSI layout design

Mohd. Hani, Mohamed Khalil and Shaikh Husin, Nasir (2009) An optimization algorithm based on grid-graphs for minimizing interconnect delay in VLSI layout design. Malaysian Journal of Computer Science, 22 (1). pp. 19-33. ISSN 0127-9084

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Abstract

In this paper, we describe a routing optimization algorithm based on grid-graphs for application in a deep-submicron VLSI layout design. The proposed algorithm, named S-RABILA (for Simultaneous Routing and Buffer Insertion with Look-Ahead), constructs a maze routing path, simultaneously with buffer insertion and wire sizing, taking into account wire and buffer obstacles, such that the interconnect delay from source to sink is minimized. In current nanometer VLSI layout design, the interconnect delay has become the dominant factor affecting system performance. Research has shown that routing algorithms, which include simultaneous buffer insertion and wire-sizing, have been proven to be very effective in solving the timing optimization problem in VLSI interconnect design. A key contribution of this work is a novel look-ahead scheme applied to speed up the runtime of the algorithm, and aids in finding the exact solution. Hence, the algorithm is accurate, fast, scalable with problem size, and can handle large routing graphs. Experimental results show the effectiveness of the look-ahead scheme and indicate that S-RABILA provides significant performance improvements over similar existing VLSI routing algorithms.

Item Type:Article
Uncontrolled Keywords:buffer insertion, elmore delay, interconnect optimization, VLSI routing
Subjects:Q Science > QA Mathematics > QA75 Electronic computers. Computer science
T Technology > TK Electrical engineering. Electronics Nuclear engineering
Divisions:Electrical Engineering
ID Code:12990
Deposited By: Ms Zalinda Shuratman
Deposited On:12 Jul 2011 01:34
Last Modified:12 Nov 2012 03:17

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