Universiti Teknologi Malaysia Institutional Repository

An AES tightly coupled hardware accelerator in an FPGA-based Embedded processor core

Mohd. Hani, Mohamed Khalil (2009) An AES tightly coupled hardware accelerator in an FPGA-based Embedded processor core. In: Proceedings - 2009 International Conference on Computer Engineering and Technology, ICCET 2009. Article number 4769658, 2 . IEEE Explore, Singapore, pp. 521-525. ISBN 978-076953521-0

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Official URL: http://dx.doi.org/10.1109/ICCET.2009.248

Abstract

This paper presents the implementation of a tightly coupled hardware architectural enhancement to the Altera FPGA-based Nios II embedded processor. The goal is to accelerate Advanced Encryption Standard (AES) operations in 128, 192 and 256-bits, for application in a high-performance embedded system implementing symmetric key cryptography. The concept is to augment the embedded processor with a new custom instruction for encryption and decryption operations. In order to show the effectiveness of tightly coupled hardware implementation over coprocessor based approach, we have also realized the design in coprocessor approach using the same AES core. Experimental results show that for the encryption or decryption operations, real implementation with custom instructions and tightly coupled hardware is about 35% faster than the co-processor based hardware.

Item Type:Book Section
Uncontrolled Keywords:advanced encryption standard, architectural enhancement, co-processor, custom instruction, decryption operations, embedded processors, encryption and decryption
Subjects:T Technology > TA Engineering (General). Civil engineering (General)
T Technology > TK Electrical engineering. Electronics Nuclear engineering
Divisions:Electrical Engineering
ID Code:12962
Deposited By: Ms Zalinda Shuratman
Deposited On:07 Jul 2011 08:46
Last Modified:07 Jul 2011 08:46

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