Mohd. Hani, Mohamed Khalil and Irwansyah, Arif and Hau, Yuan Wen (2009) A tightly coupled finite field arithmetic hardware in an FPGA-based embedded processor core for elliptic curve cryptography. International Journal of Information and Communication Technology, 2 (1-2). pp. 60-72. ISSN 1466-6642
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Official URL: http://dx.doi.org/10.1504/IJICT.2009.026430
This work presents the implementation of a tightly-coupled hardware architectural enhancement to the Altera FPGA-based Nios II embedded processor. The goal is to accelerate finite field arithmetic operations in the binary fields of F2163 and F2193, for application in a high-performance embedded system implementing elliptic curve cryptography (ECC). The concept is to augment the embedded processor with a few custom instructions for fast finite field arithmetic operations. Instead of a coprocessor, hardware acceleration of the arithmetic operation is provided by custom logic tightly coupled to the processor core and directly controlled by the instruction stream. This concept, which may be considered as a hardware-software co-design approach, is evaluated by prototyping an elliptic curve cryptosystem (ECC) on an Altera Stratix FPGA development board. Experimental results shows that for the point multiplication operation, which is the core operation in an ECC computation, the implementation with custom instructions and tightly-coupled hardware is about 50% faster than the coprocessor-based hardware.
|Uncontrolled Keywords:||custom instruction, ECC, elliptic curve cryptography, embedded processor, finite field arithmetic, FPGA, hardware-software codesign, tightly-coupled hardware|
|Subjects:||T Technology > TK Electrical engineering. Electronics Nuclear engineering|
|Deposited By:||Ms Zalinda Shuratman|
|Deposited On:||05 Jul 2011 10:04|
|Last Modified:||30 Aug 2012 03:26|
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