A'Ain, Abu Khari and Sim, Kian Sin and Cheow, Kwee Sion (2004) The effects of gate oxide short in 6-transistors SRAM cell. In: Proceedings ICSE 2004 - 2004 IEEE International Conference on Semiconductor Electronics. IEEE, USA, pp. 122-126. ISBN 978-078038658-7
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Official URL: http://dx.doi.org/10.1109/SMELEC.2004.1620852
The effects of gate oxide short (GOS) in a single 6-MOS transistors SRAM cell are studied in this work, through SPICE simulation. Both uni-directional split model and bi-dimensional lumped-transistors model are used to model the GOS in NMOS for comparison. It is assumed that only one NMOS is defective at a time. TSMC 0.18µm process parameters are used in the SPICE simulations. Interesting findings and results showed that GOS may leave catastrophic impacts on SRAM operations.
|Item Type:||Book Section|
|Additional Information:||2004 IEEE International Conference on Semiconductor Electronics, ICSE 2004, 4-9 Dec. 2004, Kuala Lumpur.|
|Uncontrolled Keywords:||electric conductivity, gates (transistor), semiconductor materials, static random access storage, transistor transistor logic circuits, GOS, lumped-transistors model, NMOS, split model, SRAM, transistors|
|Subjects:||T Technology > TK Electrical engineering. Electronics Nuclear engineering|
|Deposited By:||Liza Porijo|
|Deposited On:||12 Mar 2011 23:24|
|Last Modified:||20 Jul 2011 10:03|
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