Hybrid non scan with built-in self-test for fault coverage improvement

Abstract

Conventional design for testability (DFT) method that implements scan designs requires long test application time and costly automatic test equipment (ATE). On the other hand, built-in self-test (BIST) methods reduce the test time, but with low fault coverage. In this paper, we propose a DFT method that combines two DFT methods which is BIST and a non scan method in order to improve the fault coverage at register transfer level (RTL). BIST architecture with a standard linear feedback shift register (LFSR) is implemented as the test pattern generator. Non scan method is implemented to tackle the problem of poor testability at the internal circuit. R-graph that represents the connection of the circuit is used to derive the circuit at RTL. The self-loop register from the generated R-graph is selected so that the thru function is added to the self-loop in order to improve the testability of the circuit. The performance of the proposed DFT method will be measured on several circuits to show the effectiveness of the proposed DFT method using Synopsys tool. It will be compared to a stand-alone BIST method in terms of fault coverage. Stuck-at fault is considered as fault modeling using Tetramax tool. The results show that the proposed DFT method achieves higher fault coverage compared to the stand-alone BIST method.