Design and modeling of on-chip planar capacitor for RF application

Abstract

On-chip radio frequency (RF) capacitor is one of the key components for RF integrated circuit (RFIC) designs such as filters and oscillators. Several researches on the design of on-chip planar capacitor have been reported. However there is a need to modify the existing synthesizing procedure; model and optimize the on-chip RF capacitor. Quality factor is the essential parameter as it is an index for the efficiency of a capacitor’s performance. This thesis investigates the design of an interdigital capacitor configuration. Geometry design variables include number of fingers, finger length, finger width, finger gap, end gap, terminal width, strip thickness, substrate height, metal types and dielectric constant. The physical model of an interdigital capacitor was determined and its equivalent lumped circuit simulations have been performed. Then the optimum capacitance of the capacitor was determined. Several parameter variations on the interdigital capacitor were investigated. The effects of parameter variations on quality factor and capacitance value were discussed. An optimized interdigital capacitor can be obtained through their performance. The design has sufficient capacitance of 0.09338 pF, quality factor of 240 and operates in the 2 to 5 GHz range.